Semiconductor-on-insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs) have demonstrated switching performance advantages over bulk MOSFETs, mainly resulting from low junction capacitance. However, the lack of body contacts on SOI MOSFETs presents serious concerns related to floating body and past performance history effects, as well as electrical instability due to self-heating.
Since floating body and history effects result in threshold voltage (Vt) mismatch and aggravated leakage currents, it is highly desirable to use body contacts in applications such as static random access memory (SRAM) cells, sense amplifiers, differential amplifiers, pass transistors and dynamic random access memory (DRAM) array transistors. Otherwise greater efforts in circuit design and device design are needed to take care of the floating body issues. Floating body effects also complicate the mapping of bulk complementary metal oxide semiconductor (CMOS) circuit designs to SOI technology.
Much prior art exists which teaches body contacted SOI structures. Some of the prior art provides connection to the body via a path under the gate conductor. Other prior art uses body-to-source ties. Still other prior art forms the back gate oxide only directly under the source/drain diffusions and leaves the channel connected to the bulk substrate. However, with the shrinking of an MOSFET's gate length, it is increasingly difficult to align the oxide under the source/drain diffusions with the connection under the gate.
Therefore, a need exits for a body contacted SOI MOSFET having a thick buried insulating region under the source/drain diffusions to preserve most of the performance advantages of SOI technology.